JSSC 2007第10期Memory0.13μmSRAM

A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM

提出一种基于施密特触发器的亚阈值10T SRAM单元，具有高噪声容限和低功耗特性。

0.13μm CMOS, 160mV, 1.56×SNM提升, 18%漏电降低, 50%读写功耗降低

施密特触发器亚阈值SRAM静态噪声容限低功耗工艺变化容忍

▸创新点1：施密特触发器设计提高静态噪声容限（电路创新）。通过引入施密特触发器的迟滞特性，显著提升SRAM单元的静态噪声容限（SNM），达到1.56倍提升（400 mV vs 传统6T），有效抑制亚阈值操作下的噪声干扰。

▸创新点2：内置工艺变化容忍性（方法创新）。利用施密特触发器的非线性特性，自动补偿工艺波动，使SNM分布在不同工艺角下保持稳定，无需额外校准电路，提升制造良率。

▸创新点3：差分操作兼容现有6T架构（系统创新）。采用10T差分结构设计，保留与传统6T SRAM相同的数据接口和时序控制逻辑，可直接替换现有设计，降低升级成本。

▸创新点4：超低电压与能效优化（电路创新）。在0.13μm CMOS工艺下实现160mV工作电压，相比6T单元降低18%漏电和50%读写功耗，数据保持电压低至150mV，突破亚阈值SRAM能效瓶颈。

Abstract

We propose a novel Schmitt Trigger (ST) based differ- ential 10-transistor SRAM (Static Random Access Memory) bitcell suitable for subthreshold operation. The proposed Schmitt trigger based bitcell achieves 1.56 higher read static noise margin (SNM) ( /68/68/61400 mV) compared to the conventional 6T cell. The robust Schmitt trigger based memory cell exhibits built-in process varia- tion tolerance that gives tight SNM distribution across the process corners. It utilizes differential operation and hence does not re- quire any architectural changes from the present 6T architecture. At iso-area and iso-read-failure probability the proposed memory bitcell operates at a lower (175 mV) /68/68with 18% reduction in leakage and 50% reduction in read/write power compared to the conventional 6T cell. Simulation results show that the proposed memory bitcell retains data at a supply voltage of 150 mV. Func- tional SRAM with the proposed memory bitcell is demonstrated at 160 mV in 0.13 m CMOS technology.