← 返回 JSSC 论文列表JSSC 2007第10期Data Converters0.11μm
A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High
提出一种混合CDR技术，结合盲采样与传统相位跟踪，显著提升抖动容忍度。
0.11μm CMOS, 1.9-3.5Gb/s, 200UI@200kHz抖动容忍, 115mW@2.4Gb/s
时钟数据恢复抖动容忍盲采样相位跟踪混合CDR
▸创新点1：混合CDR架构（盲采样+相位跟踪）是一种系统创新，通过将5倍盲采样CDR嵌入传统相位跟踪CDR中，实现了两种技术的优势互补，显著提升了整体性能。
▸创新点2：抖动容忍度乘积效应是方法创新，通过混合架构的协同作用，使得低频抖动容忍度提升32倍（200 UI峰峰值@200kHz），同时保持高频抖动容忍度。
▸创新点3：高频抖动容忍保持是电路创新，采用5倍盲采样结构确保高频段（>环路滤波器带宽）的抖动抑制能力，实测BER<10^-12验证了可靠性。
▸创新点4：宽范围速率适应性（1.9-3.5Gb/s）是系统级创新，通过可配置时钟恢复方案实现，在115mW功耗下覆盖多标准应用场景。
Abstract
A hybrid CDR is presented that embeds a 5 blind-oversampling CDR within a conventional phase-tracking CDR. This hybrid CDR has a jitter tolerance that is the product of the individual jitter tolerances. In this implementation, the jitter tolerance of a phase-tracking CDR alone is increased by a factor of 32 at frequencies below its loop filter’s bandwidth, while maintaining the high-frequency jitter tolerance of a 5 blind-oversampling CDR. Measured data from a 0.11 m CMOS test chip at 2.4 Gb/s confirm a 200 UI peak-to-peak jitter toler- ance for a 200 kHz jitter. The test chip operates from 1.9 Gb/s to 3.5 Gb/s with a BER less than 10 /49/49, consuming 115 mW at 2.4 Gb/s.