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A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC
一款适用于能源受限应用的8位逐次逼近ADC，采用0.18μm CMOS工艺，实现低功耗与高带宽。
0.18μm CMOS, 0.9V, 200kS/s
逐次逼近ADC低功耗自举开关有效分辨率带宽信噪失真比
▸仅使用一个自举开关实现宽有效分辨率带宽
▸在0.9V供电下实现47.4dB的信噪失真比
▸功耗仅为2.47μW，每转换步长能耗65fJ
Abstract
An 8-bit successive approximation (SA) analog-to- digital converter (ADC) in 0.18 m CMOS dedicated for en- ergy-limited applications is presented. The SA ADC achieves a wide effective resolution bandwidth (ERBW) by applying only one bootstrapped switch, thereby preserving the desired low power characteristic. Measurement results show that at a supply voltage of 0.9 V and an output rate of 200 kS/s, the SA ADC performs a peak signal-to-noise-and-distortion ratio of 47.4 dB and an ERBW up to its Nyquist bandwidth (100 kHz). It consumes 2.47 W in the test, corresponding to a figure of merit of 65 fJ/conversion-step.