← 返回 JSSC 论文列表JSSC 2007第10期Data Converters0.18μmPipeline ADCTime-Interleaved ADC
A CMOS 15-bit 125-MS/s Time-Interleaved ADC With Digital
一款采用数字后台校准的15位125MS/s时间交织ADC，在0.18μm CMOS工艺下实现高动态范围。
0.18μm CMOS, 1.8V, 125MS/s, 91.9dB SFDR, 69.9dB SNDR
时间交织ADC数字校准CMOS采样保持放大器流水线ADC
▸采用预充电电路配置的单采样保持放大器
▸数字后台校准技术校正增益和偏移失配
▸两通道时间交织流水线ADC设计
Abstract
A 15-bit 125-MS/s two-channel time-interleaved pipelined ADC is fabricated in a 0.18 m CMOS technology, and achieves 91.9 dB SFDR, 69.9 dB SNDR for a 9.99 MHz input. This ADC incorporates a single sample-and-hold amplifier which em- ploys a precharged circuit configuration to mitigate performance requirements for its opamp. Digital background calibration is applied to maintain the conversion linearity of each A/D channel and also correct both gain and offset mismatches between the two channels. Excluding I/O buffers, the chip occupies an area of 4.3 4.3 mm/50and dissipates 909 mW from a 1.8 V supply.