A Power-Efficient Clock and Data Recovery Circuit in 0.18 /22m CMOS Technology for Multi-Channel Short-Haul Optical

Abstract

This paper studies the specifications of gated-oscil- lator-based clock and data recovery circuits (GO CDRs) designed for short haul optical data communication systems. Jitter toler- ance (JTOL) and frequency tolerance (FTOL) are analyzed and modeled as two main design parameters for the proposed topology to explore the main tradeoffs in design of low-power GO CDRs. Based on this approach, a top-down design methodology is pre- sented to implement a low-power CDR unit while the JTOL and FTOL requirements of the system are simultaneously satisfied. Using standard digital 0.18 m CMOS technology, an 8-channel CDR system has been realized consuming 4.2 mW/Gb/s/channel and occupying a silicon area of 0.045 mm /50/channel, with the total aggregate data bit rate of 20 Gb/s. The measured FTOL is 3.5% and no error was detected for a 2 /51/49 1 pseudo-random bit stream (PRBS) input data for 30 minutes, meaning that the bit error rate (BER) is smaller than 10 /49/50. Meanwhile, a shared-PLL (phase-locked loop) with a wide tuning range and compensated loop gain has been introduced to tune the center frequency of all CDR channels to the desired value.