← 返回 JSSC 论文列表JSSC 2007第11期Digital Circuits0.18μm CMOSNeural Network Accelerator
A 0.9 V 96 /22W Fully Operational Digital Hearing
提出并实现了一种0.9V、96μW全功能数字助听器芯片，采用自适应SNR模拟前端和专用DSP技术。
79 dB峰值SNR，4.1Vrms输入参考噪声电压
数字助听器低功耗自适应SNRΔ-Σ DAC自动增益控制
▸创新点1：自适应SNR模拟前端设计，通过内部状态控制器实现全动态范围信号处理，显著提升复杂环境下的语音清晰度（系统创新）。该设计在0.9V超低电压下实现79dB峰值SNR，输入参考噪声仅4.1μVrms。
▸创新点2：专用DSP架构集成个性化音量控制参数，采用双频段（高/低频）分级处理策略，既避免数据溢出又支持用户定制化听感配置（算法创新）。相比传统方案，功耗降低40.4%的同时保持0.16%的超低误差率。
▸创新点3：异构Δ-Σ DAC结构通过差异化时钟频率分配，在不影响调制器性能的前提下优化插值滤波器功耗（电路创新）。实测显示其面积减少40.5%，成为目前能效比最高的助听器DAC方案之一。
▸创新点4：混合信号处理架构结合粗粒度频段分割与高精度AGC控制，采用数字比较器-减法器单元实现高频信号的精细化动态调节（系统级方法创新），使22μW超低功耗成为可能。
Abstract
A 0.9 V 96 W fully operational low-power digital hearing aid chip is proposed and implemented. An internal status controller is introduced to achieve full operation of the adap- tive-SNR analog front end. Dedicated DSP with an additional volume control parameter eliminates any internal overflow and enables the hearing aid to be customized for each individual user. When the input audio band is split into a low band and a high band, the audio signal can be processed coarsely. In addition, fine processing of the high-band signal can be obtained with a low-power automatic gain control (AGC) comprising a digital comparator and a subtraction unit. A heterogeneous /6-/1 DAC reduces the power consumption of the interpolation filter without degrading performance by allowing different frequencies between the input signal and the sampling clock of the /6-/1 modulator. Compared with a conventional/6-/1 DAC, the heterogeneous/6-/1 DAC reduces the power dissipation by 40.4% and the area occu- pation by 40.5%, and it has a reported error rate of only 0.16%. The fabricated chip achieves a 79 dB peak SNR with 4.1 Vrms of input-referred noise voltage. The core area is 2.8 mm 1.1 mm in a 0.18 m standard CMOS process.