A 10–50-GHz CMOS Distributed Step Attenuator With Low Loss and Low

Abstract

This paper presents the design and measurement of a 10–50-GHz low-loss distributed CMOS step attenuator with low phase imbalance. The attenuation is controlled by 12 nMOS varistors, and the nMOS parasitics are absorbed in a synthetic transmission line to result in a wide bandwidth. The electrical distance between the varistors is explored to minimize the size of the distributed attenuator, and a method to balance the insertion phase is presented. At 33–37 GHz, the minimum attenuation state loss is 2.1 dB, and the maximum attenuation state loss is 13.0 dB. The attenuator has a maximum attenuation range of 11 dB with 0.9-dB steps (13 states). The rms phase imbalance is less than 3 at DC–50 GHz for all attenuation states. The attenuator does not consume any static power and the input 1-dB compression point is 5 dBm (defined as the 1-dB drop in the maximum atten- uation range) at 20 GHz. The total chip size excluding pads is 200 750 m/50(0.15 mm/50).