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A 14-bit 200-MHz Current-Steering DAC With Switching-Sequence Post-Adjustment Calibration
提出一种通过动态调整电流源开关顺序实现高精度DAC校准的新方法
14-bit, 200MHz, SFDR 81.5dB@1MHz, 78.1dB@2MHz
电流导向DAC开关序列调整动态校准高精度CMOS
▸创新点1：动态调整电流源开关顺序的校准方法（方法创新）。该方法通过动态重新排列电流源的开关顺序进行校准，而非传统调整电流值的方式，有效解决了随机误差问题，实现了81.5 dB的SFDR（1 MHz信号频率，100 MHz采样频率）。
▸创新点2：芯片实现后仍可进行误差校准（系统创新）。该校准方法在芯片制造后仍能通过动态调整开关序列修正误差，显著提升了生产良率和后期调试灵活性，尤其适用于高精度DAC的容错设计。
▸创新点3：显著减少电流源所需面积（电路创新）。通过优化开关序列而非增大电流源面积来保证精度，电流源模块面积仅占0.28 mm²，核心总面积压缩至3 mm²，在14-bit 200-MHz DAC中实现面积效率突破。
▸创新点4：高频性能优化（性能创新）。在200 MHz采样频率下仍保持78.1 dB的SFDR（2 MHz信号频率），验证了该方法在高频场景下的稳定性，突破了传统校准技术对高速DAC的性能限制。
Abstract
In this paper, a novel calibration method for high- accuracy current-steering DACs is presented. Different from tra- ditional calibration methods which achieves the calibration by ad- justing the current values of the current sources, our method does the calibration by dynamically rearranging the switching sequence of the current sources. Since this resequencing is performed after chip implementation, even random errors can be cancelled. In this way, the total area needed for the current sources can be greatly re- duced. The 14-bit DAC has been implemented in a standard 1P6M 0.18- m CMOS technology. The core area of the chip is around 3m m/50, among which the area of the current–source block is only 0.28 mm /50. The measured SFDR is 81.5 dB at 1 MHz signal fre- quency and 100 MHz sampling frequency. For 2 MHz signal fre- quency and 200 MHz sampling frequency, the measured SFDR is 78.1 dB.