← 返回 JSSC 论文列表JSSC 2007第11期Data Converters0.25μm CMOSDelta-Sigma ADC
A 2.5-V 14-bit, 180-mW Cascaded /6/1ADC for ADSL2+ Application
一款用于ADSL2应用的14位180mW级联61ADC设计
2.2MHz带宽下动态范围86dB，信噪失真比78dB，功耗180mW
Sigma-Delta ADCADSL2级联调制器谐振器拓扑三电平量化
▸创新点1：采用级联2-1-1调制器结构（系统创新），通过多级噪声整形技术显著提升动态范围至86 dB，同时优化了功耗与面积效率，适用于ADSL2的高带宽需求。
▸创新点2：使用谐振器拓扑的第一级设计（电路创新），有效抑制带内噪声并提高信号带宽至2.2 MHz，结合OSR=16实现78 dB的峰值信噪失真比。
▸创新点3：引入三电平量化器和双参考电压对（方法创新），通过动态切换参考电压降低非线性失真，提升量化精度，同时减少功耗至180 mW（2.5V供电）。
▸创新点4：集成片上参考电压缓冲器和数字滤波器（系统创新），在2.8 mm²面积内实现完整ADC功能，优化了整体系统的集成度与抗干扰能力。
Abstract
This paper presents a sigma-delta /40/6/1/41analog-to- digital converter (ADC) for the extended bandwidth asymmetric digital subscriber line application. The core of the ADC is a cascaded 2-1-1 /6/1 modulator that employs a resonator-based topology in the first stage, three tri-level quantizers, and two different pairs of reference voltages. As shown in the experimental result, for a 2.2-MHz signal bandwidth, the ADC achieves a dynamic range of 86 dB and a peak signal-to-noise and distortion ratio of 78 dB with an oversampling ratio of 16. It is imple- mented in a 0.25- m CMOS technology, in a 2.8 mm/50active area including decimation filter and reference voltage buffers, and dissipates 180 mW from a 2.5-V power supply.