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A 2.5 GHz All-Digital Delay-Locked Loop in 0.13 /22m CMOS Technology
一款0.13μm CMOS工艺下的2.5GHz全数字延迟锁定环，具有低抖动和快速锁定特性。
2.5 GHz, 30 mW, 0.03 mm², 14 ps peak-to-peak jitter
全数字延迟锁定环CMOS抖动抑制快速锁定晶格延迟单元
▸三态数字相位检测器抑制抖动现象
▸改进的逐次逼近寄存器控制器减少锁定时间
▸晶格延迟单元具有小延迟步长和固定固有延迟
Abstract
A 2.5 GHz, 30 mW, 0.03 mm/50, all-digital delay-locked loop (ADDLL) in 0.13 m CMOS technology is presented. The tri-state digital phase detector suppresses the dithering phenom- enon and reduces the output peak-to-peak jitter for a counter-con- trolled digital DLL. The lattice delay unit has both a small delay step and a fixed intrinsic delay of two NAND gates. A modified suc- cessive approximation register-controller reduces the locking time and allows the DLL to track the process, voltage, temperature, and load variations. This ADDLL locks in 24 cycles and has a closed- loop characteristic. The measured peak-to-peak jitter is 14 ps at 2.5 GHz.