A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs

Abstract

Several high-density SOI memory technologies uti- lizing the body floating effects have been proposed. Conditions needed for SoC memory IPs for many kinds of applications are not only performance but also suitability for platform technologies. We had reported TTRAM (Twin Transistor RAM) and ET /50RAM (En- hanced TTRAM) which are high-density capacitorless SOI-CMOS compatible memory IPs. A platform design methodology becomes the mainstream, providing QTAT and low-cost design. Now, we have upgraded the ET /50RAM with application-required functions called scalable TTRAM. This memory IP can be applied to many kinds of applications using the verify control technique with com- pact actively body-bias controlled (ABC) sense amplifier, and the unique test mode functions have also been proposed for practical usage. The test chip of 4 Mbit macro fabricated with 90 nm stan- dard SOI CMOS achieves performance of 263 MHz high-speed random access, 79 mW/4 Mb lower active power dissipation, 453 MHz data transfer of page/burst mode and lower stand-by current mode of 5 s data retention time. The scalable TTRAM can play the role of on-chip SoC memory IPs, for example, in consumer, mobile, and MPU/game applications.