Measurement and Analysis of PD-SOI Static Latches Based on Bistable-Gated-Bipolar Device

Abstract

Bistable-gated-bipolar (BGB) device is an impact- ionization based negative differential resistance (NDR) device fea- turing full process compatibility with CMOS. This paper presents measurement and analysis of the BGB-based static latches fabri- cated in a standard 0.35 m partially depleted silicon-on-insulator (PD SOI) CMOS technology. The experimental results demon- strate the static storage functionality and the minimum standby current of 0.1–1 nA per BGB device for the drain-to-source voltage ranging from 2.0 to 1.6 V. Compared with the conventional CMOS static latch in the same technology, the delay time is shortened by 100 ps, verified by measurement, SPICE simulation and analysis. As the major penalty for speed enhancement, increase in standby current prevents the BGB devices and the associated MOS switches from aggressively scaling and the BGB-based latches are suitable for large-geometry CMOS logic and ultralow-voltage dynamic threshold voltage MOSFET (DTMOS) logic with high switching activity.