A Low Reference Spurs 1–5 GHz 0.13 /22m CMOS Frequency Synthesizer Using a Fully-Sampled Feed-Forward Loop

Abstract

A wide tuning range, low phase noise and spurs, multi-gigahertz frequency synthesizer was realized in 0.13 m CMOS using a fully-sampled feed-forward loop filter. Both the integral and proportional loop filter paths use sample and hold switched-capacitor networks that completely isolate the oscillator from the charge-pump switching transients. The sampled nature of the filter, together with a digital domain implementation of the ripple-filtering pole spread the impulsive energy coming from the charge-pump current injection over several reference clock cycles, resulting in a dramatic reduction of the oscillator control signal ripple and thus a very low reference spur level. A multi-regulator PLL architecture reduces the supply injected noise and spurious tones, allowing the integration of the synthesizer on the same die with a large digital core, as required by modern single-chip receiver SoCs. PLL specifications include: /49 rms double-sided integrated phase noise from 1 kHz to 10 MHz, 85 dBc reference spurs, 80 dBc supply injected spurs, 300 750 m/50die area and 100 mW power dissipation from a single 2.5 V supply.