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Portless SRAM—A High-Performance Alternative to the 6T Methodology
提出一种无端口SRAM单元，替代传统6T设计，性能显著提升。
动态功耗降低19%，漏电功耗降低6%，静态噪声容限提升20%
SRAM无端口设计低功耗静态噪声容限五晶体管
▸创新点1：电路创新 - 提出了一种五晶体管设计的SRAM单元，完全摒弃了传统的传输晶体管端口，简化了电路结构，降低了设计复杂度。
▸创新点2：性能创新 - 通过优化电路设计，动态功耗降低了19%，漏电功耗降低了6%，显著提升了能效比。
▸创新点3：可靠性创新 - 静态噪声容限提升了20%，增强了SRAM单元的抗干扰能力，提高了存储器的可靠性。
▸创新点4：系统创新 - 提供了完整的理论分析和设计方法论，并进行了芯片级和缓存级的仿真验证，证明了新设计在实际应用中的可行性。
Abstract
A novel memory cell, termed “portless” SRAM, is presented as a direct alternative to the standard 6T design. The new cell consists of only five transistors and does not make use of any pass-transistor ports. A complete theoretical and functional analysis is presented along with a design methodology for implementing the new memory cell. In addition, simulations are presented on the cell level and on the cache level exhibiting comparative improvements on the order of 19 and 6 in dy- namic power and leakage power respectively. This is augmented by a 20% improvement in static noise margin for a comparable cell area. A test chip was fabricated, and measured results are presented demonstrating functionality of the new cell.