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40-Gb/s High-Gain Distributed Amplifiers With Cascaded Gain Stages in 0.18-/22m CMOS
提出一种新型高增益分布式放大器电路拓扑，采用级联共源共栅结构提升增益。
16.2dB/20dB增益, 33.4GHz/39.4GHz带宽, 260mW功耗@2.8V
分布式放大器CMOS级联增益宽带设计40Gbps
▸创新点1：电路创新 - 采用级联共源共栅增益单元结构，显著提升放大器增益，实现16.2 dB和20 dB的高增益性能。
▸创新点2：方法创新 - 广泛应用交错调谐技术，优化级联共源共栅和级联增益单元的设计，扩展带宽至33.4 GHz和39.4 GHz。
▸创新点3：系统创新 - 通过增益平坦度优化设计，确保放大器在宽频带内增益波动最小，提升信号传输质量。
▸创新点4：电路创新 - 在0.18-μm CMOS工艺下实现40 Gb/s的高速数据传输，功耗仅为260 mW，展示了高效能的设计。
Abstract
A novel circuit topology for high-gain distributed am- plifiers is presented in this study. Based on the conventional dis- tributed architecture, the gain cells are realized by cascading cas- code stages for gain enhancement. In addition, the stagger-tuning technique is extensively utilized in the design of the cascode stages as well as the cascaded stages, leading to significant improvement in terms of the operating bandwidth and the gain flatness. With the proposed circuit architecture, two amplifiers are implemented in a standard 0.18- m CMOS technology. The amplifier with a 3 3 configuration exhibits a gain of 16.2 dB and a 3-dB bandwidth of 33.4 GHz, while the one in a form of 2 4 demonstrates a gain of 20 dB and a bandwidth of 39.4 GHz. Consuming a dc power of 260 mW from a 2.8-V supply voltage, both circuits provide clear eye-opening with a pseudorandom bit sequence (PRBS) at 40 Gb/s.