← 返回 JSSC 论文列表JSSC 2007第12期RF & Wireless0.13μm
A Multimode Transmitter in 0.13 /22m CMOS Using Direct-Digital RF Modulator
一种基于直接数字射频调制器的多模发射机架构，集成了D/A转换、上变频、无用边带抑制等功能。
0.13μm CMOS, 1.2V, WCDMA EVM <2%, 噪声底-150 dBc/Hz
多模发射机直接数字射频调制器CMOSWCDMA功率控制
▸创新点1：直接数字射频调制器架构（方法创新） - 该论文提出了一种基于直接数字射频调制器的系统无关发射机架构，将D/A转换、上变频、无用边带抑制、功率控制和部分数字图像抑制滤波集成到单个混合信号电路块中，显著简化了传统发射机的复杂多级设计。
▸创新点2：多模支持（WCDMA、EDGE、WLAN）（系统创新） - 通过创新的架构设计，该调制器实现了对WCDMA、EDGE和WLAN等多种通信标准的兼容性，展示了其在多模通信系统中的灵活应用潜力，满足不同系统的严格要求。
▸创新点3：90 dB功率控制范围（性能创新） - 该调制器实现了90 dB的宽范围功率控制，从20 dBm到-25 dBm的信号功率范围内，WCDMA EVM小于2%，这一指标在低功耗和高线性度之间取得了优异平衡。
▸创新点4：低噪声与高能效设计（电路创新） - 在190 MHz载波偏移处，量化噪声底限为-150 dBc/Hz，同时模拟功耗在最大信号功率下仅为92 mW，信号功率降低时可进一步降至46 mW，数字功耗65 mW，展现了出色的能效比和噪声抑制能力。
Abstract
This paper presents a system-independent trans- mitter architecture based on a direct-digital RF-modulator which combines the D/A conversion, up-conversion, unwanted sideband rejection, power control, and part of the digital image-rejection filtering into a single mixed-signal circuit block. The multimode capability of the architecture is demonstrated with WCDMA, EDGE, and WLAN system requirements. The modulator achieves 90 dB of power control range and with an external power amplifier module, WCDMA EVM of less than 2% from signal powers of 20 dBm to /4325 dBm. The noise floor level defined by the quan- tization noise at 190 MHz offset from the carrier is 150 dBc/Hz measured at the output of the PA with/4325 dBm signal power. The analog power consumption with the maximum signal power level is 92 mW and scales down to 46 mW when reducing the signal level to 43 dBFS. The digital power consumption is 65 mW. The chip is implemented with a standard 0.13 m 1.2 V digital CMOS with total silicon area of 4 mm /50.