← 返回 JSSC 论文列表JSSC 2007第12期RF & Wireless0.13μm
A Single-Chip Dual-Band CDMA2000 Transceiver in 0.13 /22m CMOS
本文介绍了一种用于CDMA2000的单片双频收发器,采用0.13μm CMOS工艺,支持北美蜂窝和PCS频段。
0.13μm CMOS, 2.5V, SNR 23dB (PCS), SNR 25dB (Cell)
CDMA2000双频收发器零中频接收器直接转换发射器CMOS
▸创新点1:零中频接收器(Zero-IF Receiver)采用全集成设计,显著降低系统复杂度与功耗,支持CDMA2000双频段(Cell/PCS),实测SNR分别达25 dB和23 dB,解决了传统外差式架构的镜像干扰问题。
▸创新点2:直接转换发射器(Direct-Conversion Transmitter)集成基带缓冲器、I/Q调制器和独立频段驱动,实现动态范围90 dB,PCS频段输出功率达13.5 dBm,ACPR1指标优于57 dBc,消除传统上变频的混频器级联损耗。
▸创新点3:双频段全集成合成器与VCO(Dual-Band Synthesizers)采用单一CMOS工艺实现,支持蜂窝与PCS频段,相位噪声优化至-82 dBc/Hz @30 kHz,集成度提升同时降低芯片面积至8.4 mm²。
▸创新点4:动态模拟增益控制(AGC)技术实现90 dB动态范围,结合三阶基带滤波器,显著提升抗干扰能力,满足CDMA2000严苛的邻道泄漏比(ACLR)要求,实测指标达59 dBc(Cell频段)。
Abstract
A single-chip, dual-band transceiver for CDMA2000 is presented. The design supporting the North American cellular and PCS bands features a complete zero-IF receiver, a direct-con- version transmitter and two fully integrated synthesizers with VCOs. The analog receiver front-end comprises two self-matched wideband LNAs, a highly linear demodulator, and a third-order baseband filter. In a test version, I/Q ADCs and a digital front-end (DFE) to provide channel and matched filtering are included to demonstrate the performance of a fully integrated analog/digital line-up. Measured maximum SNR values of 23 dB and 25 dB for PCS and Cell bands, respectively, are achieved. The transmitter comprises baseband buffers and filters, an I/Q-modulator and sep- arate output drivers for each band. An analog gain control (AGC) for realization of a dynamic range 90 dB is implemented and a maximum output power of /4313.5 dBm at a total CDG4 urban current of 34 mA is achieved for the PCS band. Measured ACPR1 and /82/104/111values are 59 dBc 30 kHz and 0.998 for the Cell band and 57 dBc 30 kHz and 0.995 for the PCS band, respectively. The chip is fabricated in a 0.13 m RF-CMOS process, occupies a die size of 8.4 mm/50and operates with a 2.5 V supply.