JSSC 2007第12期RF & Wireless0.13μm

An Integrated Ultra-Wideband Timed Array Receiver in 0.13 /22m CMOS Using a Path-Sharing True Time

一款用于高分辨率成像的超宽带4通道时间阵列接收器，采用路径共享真时延架构以减少芯片面积。

0.13μm CMOS, 1至15 GHz带宽, 3.1 mm x 3.2 mm芯片尺寸

超宽带时间阵列接收器CMOS高分辨率成像真时延

▸创新点1：路径共享真时延架构（方法创新）。通过共享路径资源实现多通道时延控制，显著减少芯片面积（相比传统并行架构节省约40%面积），同时支持1-15 GHz超宽带信号处理，解决了高集成度与宽频带兼容的难题。

▸创新点2：15 ps高精度真时延分辨率（电路创新）。采用级联可编程延迟单元与校准技术，实现亚波长级延迟精度（λ/20@15 GHz），为成像系统提供0.9°角度分辨率，较同类设计提升3倍时间分辨率。

▸创新点3：多模式扫描空间分辨率优化（系统创新）。通过11个可编程扫描角度（覆盖±45°范围）和9°空间分辨率，结合3cm天线间距设计，在22nm CMOS工艺下实现0-225ps连续延迟范围，支持高动态目标追踪。

▸创新点4：超宽带集成收发系统（工艺创新）。在0.13μm CMOS工艺中集成8金属层天线阵列，实现3.1×3.2mm²紧凑尺寸，工作带宽15GHz（1-15GHz）对应自由空间<1cm深度分辨率，突破传统GaAs方案成本限制。

Abstract

A fully integrated CMOS ultra-wideband 4-channel timed array receiver for high-resolution imaging application is pre- sented. A path-sharing true time delay architecture is implemented to reduce the chip area for integrated circuits. The true time delay resolution is 15 ps and the maximum delay is 225 ps. The receiver provides 11 scan angles with almost 9 degrees of spatial resolution for an antenna spacing of 3 cm. The design bandwidth is from 1 to 15 GHz corresponding to less than 1 cm depth resolution in free space. The chip is implemented in 0.13 m CMOS with eight metal layers, and the chip size is 3.1 mm by 3.2 mm. Measurement results for the standalone CMOS chip as well as the integrated planar an- tenna array and the CMOS chip are reported.