JSSC 2007第12期Data Converters0.25μm CMOS

Multiple-Ramp Column-Parallel ADC Architectures for CMOS

本文提出了一种基于多斜坡单斜率ADC的CMOS图像传感器列并行ADC架构，显著提高了转换速度。

转换速度提高3.3倍，功耗仅增加16%

CMOS图像传感器列并行ADC多斜坡单斜率转换速度功耗优化

▸创新点1：多斜坡单斜率(MRSS) ADC架构（方法创新） - 该论文提出了一种新型的多斜坡单斜率ADC架构，通过引入多个斜坡信号来显著提高转换速度，实测显示其转换速度比传统单斜率ADC提高了3.3倍，同时仅增加16%的功耗。

▸创新点2：简单的模拟列电路设计（电路创新） - 该设计采用了极简的模拟列电路，主要包含一个模拟比较器和一些开关，这种简化设计降低了电路复杂度，同时保持了高性能，适合大规模集成在CMOS图像传感器中。

▸创新点3：可适应压缩扩展特性（系统创新） - MRSS ADC可以灵活调整为多斜坡多斜率ADC，利用图像信号中光子散粒噪声的幅度依赖性，实现压缩扩展特性，实测显示其转换速度比MRSS ADC提高了25%，同时功耗保持不变。

▸创新点4：高能效比（性能创新） - 该架构在显著提高转换速度的同时，功耗增加非常有限，实现了高能效比，适合低功耗应用的CMOS图像传感器设计。

Abstract

This paper presents a CMOS imager with a column-parallel ADC architecture based on a multiple-ramp single-slope (MRSS) ADC. Like the well-known column-level single-slope ADC, an MRSS ADC uses a very simple analog column circuit, which mainly consists of an analog comparator and some switches. A prototype imager using the MRSS ADC architecture was realized in a 0.25 m CMOS process. Measure- ments demonstrate that the conversion speed of an MRSS ADC is 3.3 higher than a single-slope ADC while dissipating only 16% more power. Furthermore, the MRSS ADC can be easily adapted to exhibit a companding characteristic, which exploits the amplitude-dependent nature of the photon shot noise present in imager signals. Measurements show that the resulting mul- tiple-ramp multiple-slope ADC is 25% faster than an MRSS ADC while dissipating the same amount of power.