A 11 GHz 12 22AMb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology W

Abstract

A low-power, high-speed SRAM macro is designed in a 65 nm ultra-low-power (ULP) logic technology for mobile applications. The 65 nm strained silicon technology improves transistor performance/leakage tradeoff, which is essential to achieve fast SRAM access speed at substantially low operating voltage and standby leakage. The 1 Mb SRAM macro features a 0.667 m/50low-leakage memory cell and can operate over a wide range of supply voltages from 1.2 V to 0.5 V. It achieves operating frequency of 1.1