← 返回 JSSC 论文列表JSSC 2008第1期Memory45nmSRAM
A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Tempe
提出一种45nm体CMOS嵌入式SRAM，通过改进辅助电路增强工艺和温度变化的抗扰性。
45nm CMOS, 1.0V, 512-Kb SRAM, 0.245μm²/0.327μm² 6-T cell
嵌入式SRAM工艺变化抗扰性温度变化抗扰性读辅助电路写辅助电路
▸采用被动电阻和复制存储器晶体管的读辅助电路，精确反映工艺和温度变化
▸基于电荷共享的分段动态电源线方案，扩大写入裕量并降低功耗和速度开销
▸辅助电路使静态噪声裕量和写入裕量分别提升100mV和35mV
Abstract
The variation tolerant assist circuits of an SRAM
against process and temperature are proposed. Passive resistances
are introduced to the read assist circuit with replica memory
transistors to lower the wordline voltage accurately reflecting the
process and temperature variations. For the sake of not only en-
larging the write margin but also reducing power consumption and
speed overhead, the divided dynamic power-line scheme based on
a charge sharing is adopted. Test chips of 512-Kb SRAM macros