A Digital 1.6 pJ/bit Chip Identification Circuit Using

Abstract

A 128-bit, 1.6 pJ/bit, 96% stable chip ID generation circuit utilizing process variations is designed in a 0.13 m CMOS process. The circuit consumes 162 nW from a 1 V supply at low readout frequencies and 1.6 W at 1 Mb/s. Cross-coupled logic gates were employed to simultaneously generate, amplify, and dig- itize the random circuit offset to create a stable unique digital chip ID code. A thorough statistical analysis is presented in order to explore the ID circuit reliability and stability. Two ID generators with different layout techniques were designed and fabricated to provide a performance comparison of power consumption, ID sta- bility, and ID statistical robustness.