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JSSC 2008第1期RF & Wireless130nm

A Reconfigurable Baseband Platform Based on an Asynchronous Network-on-Chip

提出一种基于异步片上网络的可重构基带平台,支持多标准设备开发。
130nm CMOS, 79.5mm²芯片面积
可重构基带异步片上网络多标准设备MIMO OFDMCMOS
创新点1:分布式控制和通信框架 - 采用基于消息传递的分布式控制模型,通过异步片上网络实现模块间高效通信,解决了多标准设备开发中的复杂性问题,显著提升了系统灵活性和可扩展性。
创新点2:异步片上网络(NoC)设计 - 利用异步电路技术实现低功耗和高时序收敛性,特别针对130纳米CMOS工艺的漏电和时序闭合问题进行了优化,支持实时MIMO OFDM通信技术。
创新点3:多标准支持架构 - 通过可重构基带处理单元和23个功能模块(包括ARM946ES核心、DMA引擎等)的协同设计,实现了对多种无线通信标准的动态适配,降低了硬件冗余和开发成本。
创新点4:系统级能效优化 - 结合时钟门控、电源管理策略和异步通信机制,在79.5平方毫米的芯片面积内实现了高性能与低功耗的平衡,适用于下一代纳米级CMOS技术。
Abstract
In order to face the inherent complexity of new radio access technologies and to address the development of multi-stan- dard devices, an innovative reconfigurable baseband architecture based on a distributed control and communication framework is proposed. This architecture is tailored to the possibilities and limitations of next-generation CMOS nanotechnologies in terms of leakage and timing closure. A combination of technology features, message passing control model, network-on-chip, asynchronous implementation, clocking and power reduction policies is used. The 79.5 mm /50chip was manufactured in a 130 nm CMOS tech- nology and is integrated in a prototyping platform to perform real-time experimentation of advanced MIMO OFDM based telecom techniques. It is composed of 23 functional units, such as computing intensive IPs, channel coding blocks, programmable DMA engines, an ARM946ES core, and an Ethernet interface. These elements are interconnected via an asynchronous layered Network-on-Chip using an interface that controls the communica- tion and configuration parameters during application scheduling.