← 返回 JSSC 论文列表JSSC 2008第1期Digital Circuits65nmProcessor/CPU
Design and Implementation of the POWER6 Microprocessor Benjamin Stolt Yonatan Mi
IBM POWER6处理器采用65nm SOI工艺，双核设计，频率高达5GHz，功耗低于100W。
65nm SOI, 5GHz, 100W
POWER6双核高频低功耗SOI工艺
▸创新点1：放弃传统高功耗设计方法，采用更高效的电路设计方法，显著降低了功耗，使处理器在高效能应用中功耗低于100W。
▸创新点2：采用自定义、合成、寄存器文件和SRAM设计，优化了电路性能和功耗，支持高达5 GHz的运行频率。
▸创新点3：多站点团队协作完成复杂设计，通过高效的团队管理和协作流程，确保了复杂设计在紧迫的时间表内完成。
▸创新点4：进行了详细的电气特性实验室测试，确保了电路设计在实际应用中的稳定性和可靠性。
Abstract
The IBM POWER6 processor is a dual-core,
341 mm /50, 790 million transistor chip fabricated using IBM’s
65 nm partially-depleted SOI process. Capable of running at
frequencies up to 5 GHz in high performance applications, it
can also operate under 100 W for power-sensitive applications.
Traditional power-intensive and deep-pipelining techniques used
in high frequency design were abandoned in favor of more power
efficient circuit design methodologies. The complexity and size of
POWER6, together wi