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High Speed and Low Energy Capacitively Driven On-Chip Wires
通过电容驱动芯片长线实现高速低能耗
180nm CMOS, 1.8V, 200mV/50mV摆幅
电容驱动低能耗信号预加重差分线噪声抑制
▸创新点1：电容驱动实现信号预加重（方法创新）。通过串联电容器驱动长片上导线，利用电容器的预加重效应显著提升信号传输速度，实验证明在14 mm导线上吞吐量提高了1.7倍，同时降低了能量消耗。
▸创新点2：侧壁寄生电容改善工艺跟踪（电路创新）。利用侧壁导线寄生电容作为串联电容器，不仅优化了工艺跟踪性能，还减少了驱动负载，使得驱动器可以更小，进一步降低了整体能耗。
▸创新点3：差分线降低噪声与交叉电容（系统创新）。采用扭曲和交错差分导线设计，有效降低了耦合噪声和米勒倍增的交叉电容，提升了信号完整性，适用于高密度集成电路环境。
▸创新点4：多驱动器共享目标导线实现预均衡（方法创新）。多个驱动器共享同一目标导线，结合简单的FIR滤波器实现驱动器侧预均衡，优化了信号传输质量，同时减少了能量消耗，实验显示在200 mV摆动下节能3.8倍，50 mV摆动下节能10.5倍。
Abstract
We present circuits for driving long on-chip wires
through a series capacitor. The capacitor improves delay through
signal pre-emphasis, offers a reduced voltage swing on the wire for
low energy without a second power supply, and reduces the driven
load, allowing for smaller drivers. Sidewall wire parasitics used
as the series capacitor improve process tracking, and twisted and
interleaved differential wires reduce both coupled noise as well
as Miller-doubled cross-capacitance. Multiple drivers