Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip Umesh Gajanan Nawathe, Mahmudul Hassan, King C. Yen, Ashok Kumar, Aparna Ramachandran, and

Abstract

The second in the Niagara series of processors (Niagara2) from Sun Microsystems is based on the power-ef- ficient chip multi-threading (CMT) architecture optimized for Space, Watts (Power), and Performance (SWaP) [SWap Rating /61 Performance /40Space Power/41]. It doubles the throughput performance and performance/watt, and provides 10 im- provement in floating point throughput performance as compared to UltraSPARC T1 (Niagara1). There are two 10 Gb Ethernet ports on chip. Niagara2 has eight SPARC cores, each supporting concurrent execution of eight threads for 64 threads total. Each SPARC core has a Floating Point and Graphics unit and an advanced Cryptographic unit which provides high enough band- width to run the two 10 Gb Ethernet ports encrypted at wire speeds. There is a 4 MB Level2 cache on chip. Each of the four on-chip memory controllers controls two FBDIMM channels. Niagara2 has 503 million transistors on a 342 mm /50die packaged in a flip-chip glass ceramic package with 1831 pins. The chip is built in Texas Instruments’ 65 nm 11LM triple- /86/116CMOS process. It operates at 1.4 GHz at 1.1 V and consumes 84 W.