A 0.2 V , 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-V oltage Computing

Abstract

A2 W, 100 kHz, 480 kb subthreshold SRAM oper- ating at 0.2 V is demonstrated in a 130 nm CMOS process. A 10-T SRAM cell allows 1 k cells per bitline by eliminating the data-de- pendent bitline leakage. A virtual ground replica scheme is pro- posed for logic “0” level tracking and optimal sensing margin in read buffers. Utilizing the strong reverse short channel effect in the subthreshold region improves cell writability and row decoder performance due to the increased current drivability at a longer channel length. The sizing method leads to an equivalent write wordline voltage boost of 70 mV and a delay improvement of 28% in the row decoder compared to the conventional sizing scheme at 0.2 V. A bitline writeback scheme was used to eliminate the pseudo-write problem in unselected columns.