A 15-bit Linear 20-MS/s Pipelined ADC Digitally Calibrated With Signal-Dependent Dithering

Abstract

Pseudo-random dithers have been used to measure capacitor mismatch and opamp gain errors of the pipelined analog-to-digital converter (ADC) in background and to calibrate them digitally. However, this error measurement suffers from signal range reduction and long signal decorrelation time. A signal-dependent dithering scheme allows the injection of a large dither without sacrificing the signal range and shortens the signal decorrelation time. A 1.5-bit multiplying digital-to-analog con- verter (MDAC) stage is modified for signal-dependent dithering with two additional comparators, and its capacitor mismatch and gain errors are measured and calibrated as one error. When sampled at 20 MS/s, a 15-bit prototype ADC achieves a spu- rious-free dynamic range of 98 dB with 14.5-MHz input and a peak signal-to-noise plus distortion ratio of 73 dB with 1-MHz input. Integral nonlinearity is improved from 25 to 1.3 least significant bits (LSBs) after calibrating the first six stages. The chip is fabricated in 0.18- m CMOS process, occupies an active area of 2.3 1.7 mm/50, and consumes 285 mW at 1.8 V.