JSSC 2008第2期Data Converters0.18μmOp-Amp

A 18-V 22-mW 10-bit 30-MSs Pipelined CMOS ADC for Low-Power Subsampling Applicat

一款低功耗18V 22mW 10位30MS/s流水线ADC，适用于子采样应用

0.18μm CMOS, 1.8V, 30MS/s, 21.6mW, 9.1 ENOB

流水线ADC子采样放大器共享门自举开关低功耗

▸采用功率高效的放大器共享架构

▸使用新型配置避免专用采样保持放大器

▸对称门自举开关增强采样线性度

Abstract

This paper describes a 10-bit 30-MS/s subsampling pipelined analog-to-digital converter (ADC) that is implemented in a 0.18 m CMOS process. The ADC adopts a power efﬁcient ampliﬁer sharing architecture in which additional switches are in- troduced to reduce the crosstalk between the two opamp-sharing successive stages. A new conﬁguration is used in the ﬁrst stage of the ADC to avoid using a dedicated sample-and-hold ampliﬁer (SHA) circuit at the input and to avoid the matching requirement betwe