A Digital Calibration Technique for Charge Pumps in Phase-Locked Systems

Abstract

A digital technique is adopted to calibrate the current mismatch of the charge pump (CP) in phase-locked systems. In this digital calibration technique, there is no extra replica CP needed. In addition, it can calibrate the CP under different control volt- ages on the loop filter to be immune to the channel-length mod- ulation. Due to the digital nature, the additional power consump- tion and digital switching noise from the calibration circuits are turned off once the calibration is finished. A 5 GHz frequency syn- thesizer is used to justify the proposed calibration technique. The measured output spur is suppressed by 5.35 dB at 5.2 GHz after the calibration circuits are active. The measured output spur levels are less than 68.5 dBc throughout the whole output frequency range. The measured phase noise is 110 dBc/Hz at an offset frequency of 1 MHz.