← 返回 JSSC 论文列表JSSC 2008第2期Power Management0.18μm CMOSCharge PumpNeural Network Accelerator
A High Linearity Fast-Locking Pulsewidth Control Loop With Digitally Programmabl
提出一种高线性度快速锁定脉宽控制环路，具有宽范围输入输出占空比和低功耗特性。
1MHz-1.3GHz, 30%-70%占空比可调, 4.8mW功耗, 13.2ps峰峰值抖动
脉宽控制环路高线性度快速锁定数字可编程低功耗
▸采用线性控制级（CS）和数字控制电荷泵（DCCP）
▸互补架构设计减少锁定时间比至4.5
▸宽范围输入输出占空比可编程控制
Abstract
A high linearity pulsewidth control loop (PWCL) is
proposed in this paper. Using the linear control stage (CS) and dig-
ital-controlled charge pump (DCCP), the proposed PWCL can be
operated within a wide-range of both input and output duty cycles
over a wide frequency range. A simple detection circuit is utilized
to control the DCCP in a complementary architecture such that the
proposed PWCL can reduce the locking time ratio to 4.5. The test
chip is fabricated using 0.18
m CMOS process. The meas