JSSC 2008第2期Memory0.13μmSRAM

A Low-Power SRAM Using Bit-Line Charge-Recycling

提出一种利用位线电荷回收的低功耗SRAM设计，显著降低写入功耗。

0.13μm CMOS, 32Kbits (256x128), 88%功耗降低

低功耗SRAM电荷回收位线写入功耗

▸创新点1：位线电荷回收技术（方法创新）。通过相邻位线电容的电荷回收实现差分电压摆动，替代传统电源线供电，显著降低写入功耗。

▸创新点2：降低写入功耗（电路创新）。采用电荷回收技术，在0.13μm CMOS工艺下实现写入周期总功耗降低88%，大幅提升能效。

▸创新点3：差分电压摆动优化（系统创新）。通过电荷回收机制优化位线电压摆动，有效避免写入失败，提升SRAM的可靠性和稳定性。

▸创新点4：测试验证与性能指标（系统创新）。通过32Kbits测试芯片验证，在多种电压和频率条件下均表现出优异的功耗优化效果，具备实际应用价值。

Abstract

Low-power SRAM design is crucial since it takes a large fraction of total power and die area in high-performance processors. Reducing voltage swing of the bit-line is an effective way to save the power dissipation in write cycles. Voltage swing reduction of bit-lines is, however, limited due to possible write-fail- ures. We propose a new low-power SRAM using bit-line Charge Recycling (CR-SRAM) for the write operation. In the proposed write scheme, differential voltage swing of a bit-line is obta