← 返回 JSSC 论文列表JSSC 2008第2期Power Management0.13μmNeural Network Accelerator
A Sub-Picosecond Resolution 0.5–1.5 GHz Digital-to-Phase Converter
提出一种新型数字相位转换器架构，实现高分辨率且不受工作频率和上升时间影响。
0.5-1.5 GHz, DNL<0.1 ps, INL<12 ps, 15 mW@1 GHz
数字相位转换器亚皮秒分辨率delta-sigma调制相位锁定环延迟锁定环
▸采用delta-sigma调制器对PLL生成的8相位进行抖动处理
▸利用延迟锁定环相位滤波器滤除高频截断误差
▸实现亚皮秒级分辨率和低非线性误差
Abstract
A digital-to-phase converter (DPC) is an essential building block in applications such as source-synchronous inter- faces and digital phase modulators. The resolution of DPCs using analog phase interpolators is severely affected by the operating frequency and rise times of the interpolator inputs. In this paper, we present a new DPC architecture that achieves high resolution independent of both the operating frequency and the rise time. The 8 phases generated by a phase-locked loop are dithered using a delta-sigma modulator to shape the truncation error to high frequency and is subsequently filtered using a delay-locked loop phase filter. The test chip, fabricated in a 0.13 m CMOS process, operates from 0.5–1.5 GHz and achieves a differential nonlinearity of less than 0.1 ps and an integral nonlinearity of 12 ps. The total power consumption while operating at 1 GHz is 15 mW.