← 返回 JSSC 论文列表
📄 下载 JSSC 原文 PDF
JSSC 2008第2期Clocking & PLLsPLL

Fast-Lock Hybrid PLL Combining Fractional-/78and Integer-/78Modes of

提出一种混合PLL,结合分数和整数模式,实现快速锁定和设计简化。
混合PLL快速锁定分数模式整数模式带宽切换
单环PLL在锁相时采用窄带宽整数模式,瞬态时采用宽带宽分数模式
混合PLL同时具备分数PLL的快速锁定和整数PLL的设计简单性
频率分频模式切换实现更数字化的带宽切换协议
Abstract
We introduce a single-loop PLL that operates in a narrower-bandwidth, integer- mode during phase lock and in a wider-bandwidth, fractional- mode during transient. This hybrid PLL, as a generalization of the conventional variable-band- width PLL that shifts only its bandwidth, simultaneously achieves the fast-locking advantage of the fractional- PLL and design simplicity of the integer- PLL, and as such, brings benefits in certain important PLL applications. In addition, the frequency division mode switching, unique in the hybrid PLL, enables a new, more digital protocol to execute bandwidth switching. A CMOS IC prototype attests to the validity of the proposed approach.