40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS

Abstract

High-speed front-end amplifiers and CDR circuits play critical roles in broadband data receivers as the former needs to perform amplification at high data rate and the latter has to re- time the data with the extracted low-jitter clock. In this paper, the design and experimental results of 40 Gb/s transimpedance-AGC amplifier and CDR circuit are described. The transimpedance am- plifier incorporates reversed triple-resonance networks (RTRNs) and negative feedback in a common-gate configuration. A math- ematical model is derived to facilitate the design and analysis of the RTRN, showing that the bandwidth is extended by a larger factor compared to using the shunt-series peaking technique, especially in cases when the parasitic capacitance is dominated by the next stage. Operating at 40 Gb/s, the amplifier provides an overall gain of 2 /107/10and a differential output swing of /53/50/48/109/86/112/112 with BER /49/48 /57for input spanning from /52/51/48 A/112/112to /52mA/112/112. The measured integrated input-referred noise is /51 /51 A/114/109/115. The half-rate CDR circuit employs a direction-determined rotary-wave quadrature VCO to solve the bidirectional-rotation problem in conventional rotary-wave oscillators. This guarantees the phase sequence while negligibly affecting the phase noise. With 40 Gb/s /50/51/49 /49PRBS input, the recovered clock jitter is /48 /55ps/114/109/115 and /53 /54ps/112/112. The retimed data exhibits /49/51 /51ps/112/112jitter with BER /49/48 /57. Fabrica