A Noise Reduction and Linearity Improvement Technique for a Differential Cascode LNA

Abstract

A typical common source cascode low-noise amplifier (CS-LNA) can be treated as a CS-CG two stage amplifier. In the published literature, an inductor is added at the drain of the main transistor to reduce the noise contribution of the cascode transis- tors. In this work, an inductor connected at the gate of the cas- code transistor and capacitive cross-coupling are strategically com- bined to reduce the noise and the nonlinearity influences of the cas- code transistors in a differential cascode CS-LNA. It uses a smaller noise reduction inductor compared with the conventional inductor based technique. It can reduce the noise, improve the linearity and also increase the voltage gain of the LNA. The proposed technique is theoretically formulated. Furthermore, as a proof of concept, a 2.2 GHz inductively degenerated CS-LNA was fabricated using TSMC 0.35 m CMOS technology. The resulting LNA achieves 1.92 dB noise figure, 8.4 dB power gain, better than 13 dB S11, more than 30 dB isolation (S12), and 2.55 dBm IIP3, with the core fully differential LNA consuming 9 mA from a 1.8 V power supply.