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A Wide-Range Mixed-Mode DLL for a Combination 512 Mb 20 Gbspin GDDR3 and 25 Gbsp
本文提出了一种用于512 Mb图形SDRAM的混合模式延迟锁定环（MDLL），通过时钟分频和模拟相位生成扩展了锁频范围。
1.5 V 95 nm CMOS, 1 GHz时钟, RMS抖动4.6 ps, 峰峰值抖动38 ps, 功耗107 mW
混合模式延迟锁定环时钟分频模拟相位生成低功耗时钟分配网络图形SDRAM
▸混合模式延迟锁定环（MDLL）
▸时钟分频和模拟相位生成（APG）
▸低功耗时钟分配网络（CDN）
Abstract
A mixed-mode delay-locked loop (MDLL) for a
512 Mb graphics SDRAM is presented in this paper. The MDLL
extends its lock range into the gigahertz realm by applying
clock division and analog phase generation (APG). The divided
clock from the MDLL is used for clocking logic and tracking
deterministic access latency in the SDRAM. A short discussion
of some of the side effects and advantages of using a divided,
multi-phase clock for logic operation is presented. A low-power
clock distribution network