JSSC 2008第3期Other0.13μm

An 8.29 mm/5052 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 /22m CMOS Process Xin-Yu Shih, Cheng-Zhou Zhan, Cheng-Hung Lin, and An-Yeu (Andy) Wu

本文提出了一种用于移动WiMAX系统的多模式LDPC解码器设计。

TSMC 0.13μm CMOS, 1.2V, 83.3MHz, 52mW

LDPC解码器移动WiMAX多模式设计重叠操作早期终止

▸创新点1：基矩阵重排序（方法创新） - 通过重新排列基矩阵的结构，优化了LDPC解码器的数据流路径，减少了内存访问冲突，提升了硬件效率，具体实现了从50%到75%的硬件利用率提升。

▸创新点2：主计算单元重叠操作（系统创新） - 采用重叠操作机制，使得解码过程中的多个计算单元能够并行工作，显著降低了解码延迟至非重叠方法的68.75%，同时提高了整体吞吐量。

▸创新点3：早期终止策略（方法创新） - 动态调整迭代次数，根据信道信噪比（SNR）实时优化解码过程，既保证了解码精度，又减少了不必要的计算开销，从而降低了功耗（52 mW）。

▸创新点4：多模式设计策略（系统创新） - 支持Mobile WiMAX系统中19种不同的块大小模式（如576至2304），通过灵活的硬件架构实现多模式兼容，核心面积仅4.45 mm²，展现了高度集成的设计能力。

Abstract

This paper presents a multi-mode decoder design for Quasi-Cyclic LDPC codes for Mobile WiMAX system. This chip can be operated in 19 kinds of modes speciﬁed in Mobile WiMAX system, including block sizes of 576, /46/46/46, 2304. There are four pro- posed design techniques: reordering of the base matrix, overlapped operations of main computational units, early termination strategy and multi-mode design strategy. Based on overlapped decoding mechanism, the decoding latency can be reduced to 68.75% of non- overlapped method, and the hardware utilization ratio can be en- hanced from 50% to 75%. Besides, the proposed early termina- tion strategy can dynamically adjust the number of iterations when dealing with communication channels of different SNR values. The proposed multi-mode LDPC decoder design is implemented and fabricated in TSMC 0.13 m 1.2 V 1P8M CMOS technology. The maximum operating frequency is measured 83.3 MHz and the cor- responding power dissipation is 52 mW. The core size is 4.45 mm /50 and the die area only occupies 8.29 mm /50.