← 返回 JSSC 论文列表JSSC 2008第4期Data Converters0.13 µm CMOSTime-Interleaved ADC
A 135 GSs 10 b 175 mW Time-Interleaved AD Converter in 013 µm CMOS
介绍了一种16通道时间交织ADC，结合高采样率和良好能效，采用超前逻辑减少延迟。
1.35 GS/s, 7.7 ENOB, 1 GHz ERBW, 0.6 pJ/step FoM
时间交织ADC超前逻辑能效优化高速采样时序对齐
▸单侧过范围架构提高25%能效
▸超前逻辑最小化SA-ADC逻辑延迟
▸三种技术提升T&H带宽和线性
Abstract
ten V ertregt, Member , IEEE, and
Bram Nauta, Fellow, IEEE
Abstract—A time-interleaved ADC is presented with 16 chan-
nels, each consisting of a track-and-hold (T&H) and two succes-
sive approximation (SA) ADCs in a pipeline configuration to com-
bine a high sample rate with good power efficiency. The single-
sided overrange architecture achieves a 25% higher power effi-
ciency of the SA-ADC compared with the conventional overrange
architecture, and look-ahead logic is used to minimize logic delay