A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunit

Abstract

kura, Marefusa Kurumada, Toshio Terano, Y oshinobu Y amagami, Naoki Kotani, Katsuji Satomi, Koji Nii, Member , IEEE, Makoto Y abuuchi, Y asumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara, and Hironori Akamatsu , Member , IEEE Abstract—We propose a new 2-port SRAM with a single read bit line (SRBL) eight transistors (8T) memory cell for a 45 nm system-on-a-chip (SoC). Access time tends to be slower as a fab- rication is scaled down because of threshold volt