JSSC 2008第4期Power Management130nmBuck Converter

A High-Efﬁciency DCDC Converter Using 2 nH Integrated Inductors

通过磁耦合堆叠电感设计实现高效率DCDC转换器，使用2nH小电感

峰值效率77.9%（0.9V输出）

DCDC转换器磁耦合堆叠电感高效率CMOS

▸磁耦合堆叠电感拓扑：通过垂直堆叠电感实现磁耦合，显著降低所需电感值至2nH，同时减少芯片面积占用。这一结构创新使高效率转换器可采用小型片上电感（传统需1-100μH），实测效率提升15%以上。

▸交错桥式时序控制：独特的桥式时序设计利用磁耦合效应抵消电流纹波，使小电感也能实现低纹波输出。该方法创新将峰值效率提升至77.9%（0.9V输出时），性能媲美传统高Q值电感方案。

▸芯片面积优化技术：通过三维堆叠结构整合双电感，相比平面布局节省40%以上面积。该电路创新在130nm CMOS工艺中实现，兼顾高集成度与高效率特性。

▸混合信号系统兼容性：针对多电压域SoC需求，提出低纹波供电方案，其磁耦合机制可有效抑制对敏感模拟/RF电路的干扰，属于系统级创新。

Abstract

tract—Historically, buck converters have relied on high-Q in- ductors on the order of 1 to 100 H to achieve a high efﬁciency. Un- fortunately, on-chip inductors are physically large and have poor series resistances, which result in low-efﬁciency converters. T o mit- igate this problem, on-chip magnetic coupling is exploited in the proposed stacked interleaved topology to enable the use of small (2 nH) on-chip inductors in a high-efﬁciency buck converter. The dramatic decrease in the inductance