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A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS
一篇关于65纳米CMOS工艺下可扩展低功耗I/O收发器的IEEE JSSC论文，支持5-15 Gbps操作。
65 nm CMOS, 5–15 Gbps, 2.8–6.5 mW/Gbps
低功耗I/O高速I/O电源效率优化电感终止被动均衡
▸可扩展的收发器电路块
▸联合优化电源电压、偏置电流和驱动器功率与数据速率
▸通过电感链路终止实现被动均衡
Abstract
, IEEE, Gaurab Banerjee , Senior Member , IEEE,
James E. Jaussi , Member , IEEE, Mozhgan Mansuri, Frank O’Mahony, Bryan Casper, and
Randy Mooney, Member , IEEE
Abstract—We present a scalable low-power I/O transceiver in
65 nm CMOS, capable of 5–15 Gbps operation over single-board
and backplane FR4 channels with power efficiencies between
2.8–6.5 mW/Gbps. Nonlinear power–performance tradeoff is
achieved by the use of scalable transceiver circuit blocks and joint
optimization of the supply voltage,