A Sub-600-mV , Fluctuation Tolerant 65-nm CMOS SRAM Array With Dynamic Cell Biasing Azeez J. Bhavnagarwala , Member , IEEE

Abstract

Fluctuation limitations on scaling CMOS SRAM cell transistor dimensions and operating voltages are demonstrated by measuring local stochastic distributions of 65-nm PDSOI CMOS SRAM cell storage node voltages during Read, Write, and Reten- tion modes of operation. These measurements reveal insights into terminal voltage dependencies of cell margin distributions—obser- vations that are engaged to increase cell immunity to random /86/84 fluctuations by several orders of magnitude by biasing the cell ter- minal voltages dynamically with a Read-Write asymmetry. Com- binations of circuit techniques implementing these dynamic cell biasing schemes are demonstrated in a 9kb 74b PDSOI CMOS SRAM array with a conventional 65 nm SRAM cell and an ABIST. Measurements demonstrate these techniques to enable /86/77/73/78re- ductions of over 200 mV—lowering measured /86/77/73/78to 0.54 V and 0.38 V/0.50 V for single and dual implementations, respectively. The techniques consume a 10%–12% overhead in area, impact performance marginally ( 5%) and also enable over 50% reduc- tion in cell leakage.