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JSSC 2008第4期Other60nm

A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing

提出一种新型MLC NAND页架构，通过临时LSB存储和并行MSB编程减少单元间干扰。
BL-BL干扰减少100%，WL-WL和对角干扰减少50%，编程速度提升11%
MLC NAND单元间干扰页架构并行编程临时存储
▸临时LSB存储编程方案：该方法创新通过临时存储LSB数据，在编程过程中减少单元间干扰，显著降低了BL方向的干扰达100%，同时提高了编程速度11%。
▸并行MSB编程方案：该电路创新采用并行编程技术，优化了MSB编程顺序，减少了WL方向和对角线方向的单元间干扰达50%，提升了整体编程效率。
▸BL电压调制ISPP技术：该系统创新通过调制位线电压的增量步进脉冲编程（ISPP），有效抑制了编程过程中的单元间干扰，尤其在40纳米以下技术节点中表现突出。
▸综合架构优化：结合临时LSB存储和并行MSB编程，该创新在不增加存储阵列尺寸的前提下，显著降低了单元间干扰，同时提升了编程速度和整体性能。
Abstract
h Memories Ki-Tae Park, Myounggon Kang, Doogon Kim, Soon-Wook Hwang, Byung Y ong Choi, Y eong-Taek Lee, Changhyun Kim, Senior Member , IEEE, and Kinam Kim , Fellow, IEEE Abstract—A new MLC NAND page architecture is presented as a breakthrough solution for sub-40-nm MLC NAND flash memories and beyond. To reduce cell-to-cell interference which is well known as the most critical scaling barrier for NAND flash memories, a novel page architecture including temporary LSB storing program and parallel MSB