Abstract
Montoye , Member , IEEE, Y utaka Nakamura, Kevin A. Batson,
Richard J. Eickemeyer , Senior Member , IEEE, Robert H. Dennard , Fellow, IEEE, Wilfried Haensch, and
Damir Jamsek
Abstract—An eight-transistor (8T) cell is proposed to improve
variability tolerance and low-voltage operation in high-speed
SRAM caches. While the cell itself can be designed for exceptional
stability and write margins, array-level implications must also be
considered to achieve a viable memory solution. These constraints