← 返回 JSSC 论文列表JSSC 2008第4期Digital Circuits
Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine
设计并实现了一个可配置的异构多核SoC，集成多种处理器以支持高性能和低功耗应用。
1GHz CPU, 500MHz MBMX, 512kB L2缓存, 45%功耗降低
多核SoC异构计算低功耗高性能缓存一致性
▸异构多核架构（CPU、MBMX、控制器）
▸高速多层系统总线互联
▸延迟管理网络实现1GHz CPU
Abstract
A multicore system-on-chip (SoC) has been developed
for various applications (recognition, inference, measurement, con-
trol, and security) that require high-performance processing and
low power consumption. This SoC integrates three types of syn-
thesizable processors: eight CPUs (M32R), two multi-bank matrix
processors (MBMX), and a controller (M32C). These processors
operate at 1 GHz, 500 MHz, and 500 MHz, respectively. These
three types of processors are interconnected on this chip with a
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