Abstract
Onouchi, Takashi Todaka, Takanobu Tsunoda,
Tomoyuki Kodama, Kunio Uchiyama, Senior Member , IEEE, Toshihiko Odaka, Tatsuya Kamei , Member , IEEE,
Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada , Member , IEEE, Keiji Kimura , Member , IEEE, and
Hironori Kasahara, Member , IEEE
Abstract—This paper describes a heterogeneous multi-core pro-
cessor (HMCP) architecture that integrates general-purpose pro-
cessors (CPUs) and accelerators (ACCs) to achieve exceptional per-
formance as well as