← 返回 JSSC 论文列表JSSC 2008第5期Clocking & PLLs0.13μm CMOS
A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector Che-Fu Liang S
提出一种基于GDCO相位检测器的抖动容限增强型10Gb/s时钟数据恢复电路
0.96ps RMS抖动, 7.11ps峰峰值抖动, 10Gb/s速率下BER<10^-12
时钟数据恢复抖动容限数字控制振荡器相位检测器半速率架构
▸采用级联双半速率CDR结构放宽设计瓶颈
▸基于GDCO的相位检测器实现宽线性范围
▸不牺牲抖动传递性能的前提下增强抖动容限
Abstract
n Liu , Senior Member , IEEE
Abstract—A jitter-tolerance-enhanced 10 Gb/s clock and data
recovery (CDR) circuit is presented. The proposed architecture
cascades 2 half-rate CDRs with different loop bandwidth to relax
the design bottleneck and the predicted jitter tolerance can be
enhanced without sacrificing the jitter transfer. By using a gated
digital-controlled oscillator (GDCO), the proposed GDCO-based
phase detector may reduce the cost of this architecture and achieve
a wide linear range. Th