← 返回 JSSC 论文列表JSSC 2008第6期Data Converters0.35μmDelta-Sigma ADCPLL
A 2.5-GHz DDFS-PLL With 1.8-MHz Bandwidth in 0.35- /22m CMOS Andrea Bonfanti, Davide
提出了一种宽带频率合成器架构，结合DDFS和偏移PLL，实现高频率分辨率和低相位噪声。
0.35μm CMOS, 2.5GHz, 1.8MHz带宽, 3μs settling time, 120mW PLL core, 50mW DDFS+DACs, 19mW GFSK modulator
频率合成器DDFS偏移PLL相位噪声蓝牙发射机
▸创新点1：采用DDFS控制偏移PLL输出频率，通过数字方式精确调控频率合成，避免了传统模拟调谐的非线性问题，实现了更高的频率稳定性和分辨率（24Hz）。
▸创新点2：实现24Hz频率分辨率，通过DDFS的高精度数字控制结合PLL的宽带宽特性，显著提升了频率合成的精细度，适用于高精度通信系统如蓝牙调制。
▸创新点3：扩大环路带宽至1.8MHz，通过DDFS-PLL架构避免了量化噪声对相位噪声的影响，从而允许更宽的带宽设计，提升了系统的动态响应速度和稳定性。
▸创新点4：在0.35μm CMOS工艺下实现低功耗设计，PLL核心功耗120mW，DDFS加DAC功耗50mW，GFSK调制器功耗19mW，整体功耗优化显著，适合便携式设备应用。
Abstract
A wideband frequency synthesizer architecture is presented. The proposed topology employs a direct digital fre- quency synthesizer (DDFS) to control the output frequency of an offset-PLL. In this way, the synthesizer features a very fine fre- quency resolution, 24 Hz, as in delta-sigma fractional-N PLLs, but without being affected by the quantization-induced phase noise. This, in turn, allows enlarging the loop bandwidth. The frequency synthesizer is designed to be employed as a direct modulator for Bluetooth transmitter in a low-cost 0.35- m CMOS technology. At 2.5 GHz it achieves 1.8-MHz bandwidth, while the settling time within 30 ppm for an 80-MHz step is 3 s. The integrated phase noise gives less than 1 degree of rms phase error and the worst-case spur is 48 dBc at 1 MHz, well below the specifications. Power dissipation is 120 mW for the PLL core, 50 mW for the DDFS plus DACs, and 19 mW for the GFSK modulator.