JSSC 2008第6期RF & Wireless90 nm

A 54 mW007 mm5024 GHz Front-End Receiver in 90 nm CMOS for IEEE 802154 WPAN Stan

一款符合IEEE 802.15.4标准的2.4 GHz CMOS接收器前端，采用90 nm工艺，低功耗设计。

90 nm CMOS, 1.35V, 4 mA, 35 dB转换增益, 7.5 dB NF, 10 dBm IIP3, >32 dB镜像抑制

IEEE 802.15.4低功耗CMOS接收器无源混频器集成balun

▸电感less LNA设计：采用无电感低噪声放大器（LNA）结构，通过优化晶体管级联和反馈网络实现7.5 dB噪声系数（NF），显著降低芯片面积（0.07 mm²）和功耗（4 mA @1.35V），属于电路级创新。

▸新型时钟方案驱动无源混频器：提出基于分频器（divider by two）的时钟生成架构，直接驱动被动混频器，省去传统LO缓冲级，降低功耗20%并提升相位噪声性能，属于方法创新。

▸集成balun的紧凑结构：在90 nm CMOS工艺中实现片上balun集成，将输入匹配网络与射频前端融合，总面积仅0.23 mm²，支持35 dB转换增益和32 dB镜像抑制，属于系统级集成创新。

▸低中频（low-IF）拓扑优化：采用6 MHz中频的接收机架构，结合新型信道滤波器设计，在1.35V供电下实现10 dBm IIP3线性度，平衡了功耗与抗干扰性能，属于系统架构创新。

Abstract

, Mathilde Sié, Bruno Pellat, and Thierry Parra Abstract—An integrated 2.4 GHz CMOS receiver front-end according to the IEEE 802.15.4 standard is presented in this paper. It integrates the overall RF part, from the balun up to the ﬁrst stage of the channel ﬁlter, as well as the cells for the LO signal conditioning. The proposed architecture is based on a 6 MHz low-IF topology, which uses an inductorless LNA and a new clocking scheme for driving a passive mixer. When integrated in a 90 nm CMOS te